Note that the Sub-Sample Buffer is shown here only to show the cadence of the data. The first problem is the necessity of an exclusive CPU. Shown here is a back-to-back transfer of 2 bytes from Callisto to the microprocessor on txd using a single stop bit. This circuit requires a well controlled resistor. The following table shows characteristics of the PLL:
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The description of each register is as follows. Meanwhile the internal address pointer will be increased automatically. After that the internal address pointer is increased automatically. Vsync coming , will show on the Intensity pin. Otherwise, FB pin will always drive low when window color is displaying. Bit 0 to Bit3. OSD menu and Windows will be displayed on top of this monitor background color. OSD enabled Model No.: Data port of the OSD window register. This register was the data port when access the OSD window registers.
It is very important to know the programmed range for Window 1 and Window 2 must be covered by the original visible domain, defined by OSDStartRow and EOD bit setting for the last display row. The color of the window shadow is encoded as follows: Defining the window shadow of window 4.
DE is treated as one kind of Csync Model No.: HsyncOut; if the pulse of incoming Vsync is missing, an artificial pulse will be inserted with pulse width defined by VPW. The tailing edge of VsyncOut is also close to the tailing edge of the inputted Vsync but snapped to the leading edge of HsyncOut Model No.: After 1 H line After 2 H lines After 3 H lines After 4 H lines After 5 H lines After 6 H lines After 7 H lines Model No.: The active duration of STH pulse is always one-pixel width.
Page of Go. Table of Contents Add to my manuals Add. Page 9 Reproduction Center 0. Page 10 of a 25mm diameter area, with all display pixels set to a gray level, to the luminance of that same area when any adjacent area is driven dark.
Page 14 CN21, 22, 23, Page 16 - Model No.: Page 17 - 7. Page 20 There shall not be visible light from the back-lighting system around the edges of the screen as seen from a distance 50[cm] from the screen with an overhead light level of [lux]. Page 21 8 Shock test non-operating Pulse width: Page 23 - Page 24 Figure 3.
Page 25 - Figure 5. Page 26 - Figure 6. Block Diagram - 1. Pin Description - 2. Page 34 - Memory Map Model No.: Page 37 - Reset Timing Model No.: Page 47 Timer 0: Page 48 - Model No.: Page 49 - Model No.: Page 50 The Baud rate in Mode 1 and Mode 3 can be determined by overflow rate of Timer 1, Timer 2 or both one for transmit and other for receive. Page 54 - Model No.: Page 55 - Model No.: Page 58 The M has 3 programmable lock bits that when programmed according to Table will provide different levels of protection for the on-chip code and data.
Page 60 XTAL1 signal. Page 61 - 8. Page 67 - Model No.: Page 68 - Model No.: Page 71 Data inversion control for odd pixel bus if more than half signals in the bus change state, this will be set. Page 75 - Model No.: Page 76 Display A port green data. Page 80 All timing is measured at 1.
Page 83 IHS falling edge. Page 86 The block diagram is depicted as follows: Page 97 Hstart and Hend. Page - Model No.: Page The programmable LPF can be used for noise-reduction. Page As shown in above table, there are 7 fields about the row based display attributes. Page Given by the flexibility of this mode, associated with SP code feature, it is already sufficient to create the window-like menu.
Page In total, there are 15 possible line insertion encoded by this field. Page The remaining codes represent the lines inserted between two display rows.
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Figures in this article are calculated using data from the last twelve months, which refer to the month period ending on the last date of the month the financial statement is dated.
This may not be consistent with full year annual report figures. To help readers see pass the short term volatility of the financial market, we aim to bring you a long-term focused research analysis purely driven by fundamental data. Note that our analysis does not factor in the latest price sensitive company announcements.
The author is an independent contributor and at the time of publication had no position in the stocks mentioned. Once the module of any sub algorithm is loaded into the internal RAM , this sub algorithm is executed when the microprocessor returns to the single-chip mode or the internal mode.
The first problem is the necessity of an exclusive CPU. The second problem lies in that the RAM should be of an exclusive type for the following reason. As a cache in a general-purpose CPU is capable of automatically caching a saved command or data, such a command or data in the incorporated cache is freely rewritten when an external memory is accessed. This leads to the necessity of an exclusive RAM which prevents automatic rewriting of the contents of the cache.
Another solution is to store a program commands or data in a non-cache area so that the program commands or data will not be cached. But, this scheme prevents the internal RAM from functioning as a cache in normal operation mode, the system's processing speed in normal operation mode is slowed. The third problem is that the CPU to be used itself becomes expensive because the CPU should be a special chip, not a general-purpose one, in order to avoid the first and second problems. First, the performance gets lower as the reception speed becomes lower.
That is, the second prior art is directed to a reception-only terminal and the operation clock is always reduced when the terminal is connected to a communication circuit to receive radio data.
More specifically, if this prior art is adapted to a terminal having both transmission and reception capabilities, the operation clock is decreased both in transmission mode and reception mode, the performance is significantly lowered.
Secondly, operation clocks are needed for two systems for the following reason. Most of general-purpose CPUs do not have two clock inputs, and the clocks of general-purpose CPUs which have two clock inputs are a normal operation clock and a clock for measuring the time. The frequency of the time measuring clock is about 32 KHz, which is very slow as the reference clock for radio reception.
The use of this clock leads to a considerable reduction in reception speed and is not therefore practical. In this case, an exclusive CPU equipped with another clock input becomes necessary. Thirdly, when the frequency of the reference clock is reduced or the reference clock is disabled at the time of radio reception, it takes time to return to the normal processing, resulting in a significant reduction in performance. Further, reducing the frequency of the reference clock requires that the OS Operation System should handle control of the operation of the radio unit.
Furthermore, this terminal may fail to properly receive reception data for the following reason. It takes time to adjust the timer or clock or time to stabilize the PLL Phase Locked Loop or crystal oscillator after the reduction of the clock frequency or the disabling of the reference clock, so that the reception operation cannot be initiated during such a time.
This leads to a significant reduction in performance. If the timer or the like in the OS gets wrong, the radio unit does not operate properly and some adjustment should be performed to set the radio unit in the proper operation. Such processing needs a considerable time to restore the normal reception operation, so that processing of received data may not be completed in time to catch the next data. First, this prior art copes only with the noise that is generated by the reference clock used in a radio section.
That is, while generation of noise by the CPU's access to the external bus is dominant in an actual radio portable terminal, the third prior art is directed to a measure against noise generated in the radio section and this method cannot cope with a radio portable terminal which has the radio section integrated with the CPU that performs transmission and reception of information.
Secondly, the noise that is generated by the CPU's access to the external bus has a wide frequency band. The frequency band of the noise generated by the CPU's access to the external bus has a width of several MHz, so that alight alteration of the reference clock cannot eliminate the influence of noise on the frequency band used in radio communication.
Thirdly, some radio portable terminals do not make access synchronous with the reference clock. The timing for memory access is determined by the time, not based on the reference clock.
When the operation reference clock is changed, therefore, the timing for memory access is changed and the proper memory access may not be carried out. It is not therefore possible to significantly alter the operation clock of the system. Accordingly, it is a primary object of the present invention to provide a noise reducing method for a radio portable terminal, which stores an internal operation program that does not access an external memory in a cache incorporated in a CPU in synchronism with data received by radio, and allows the radio portable terminal to be operated only with access to the internal cache at the time of radio reception, thereby reducing access to the external memory, so that noise to received data can be reduced.
It is another object of this invention to provide a noise reducing method for a radio portable terminal, which can reduce noise by masking interruption to a CPU before a predetermined program is stored in an internal cache in the CPU, thereby suppressing rewriting of a program stored in the cache and preventing access to an external memory of the CPU.
According to one aspect of this invention, there is provided a noise reducing method for a radio portable terminal having a radio section for transmitting and receiving radio data, a CPU Central Processing Unit , connected to the radio section and incorporating a cache, for performing predetermined data processing, and an external memory connected to the CPU, which method comprises the steps of reading an internal operation program runnable only in the CPU from the external memory and storing the internal operation program in the cache prior to reception of the radio data; and then executing only the internal operation program and suppressing access to the external memory during reception of the radio data, thereby reducing noise.
According to another aspect of this invention, there is provided a noise reducing method for a radio portable terminal having a radio section for transmitting and receiving radio data, a CPU, connected to the radio section, for performing data processing, and an external memory connected to the CPU, which method comprises the steps of giving a priority order to individual processes to be executed by the radio portable terminal; and masking an interruption process of low priority so as not to execute the masked interruption process at a time of receiving the radio data, thereby reducing noise at a time of receiving the radio data.
Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. This radio portable terminal comprises a CPU 10 , an oscillator 20 , a radio section 30 and an external memory The structure of the CPU 10 will now be described in detail. The CPU 10 comprises a main processing section 11 which performs data processing and analyzes and executes commands, a sub-processing section 12 which performs memory management and exception handling, a command cache 13 as a memory to store commands or a program, a data cache 14 as a memory to store data, a bus interface 15 which controls access to an external unit like a memory, a clock controller 16 which sends an operation reference clock OCLK to the individual blocks, and an interrupt controller 17 which controls an interruption from outside the CPU The sub-processing section 12 includes an address conversion buffer TLB The interrupt controller 17 masks interruptions from outside the CPU 10 according to preset conditions and gives only the necessary interruption to the sub-processing section The time chart in FIG.
The reception sync signal SYN is generated every 20 ms in synchronism with the reception timing. The operation of the radio portable terminal in FIG. Suppose that a request for reception of radio data has been made while the radio portable terminal is performing some process step S 1.
First, the main processing section 11 checks the contents of the current task step S 2. Then, the main processing section 11 checks if reception of radio data has priority over the contents of the current task step S 3.
To accomplish this check, a priority order should previously be set to the individual processes. When the current task has priority over reception of radio data N in step S 3 , the main processing section 11 resumes the current task and does not perform reception of radio data. When the process that has priority over reception of radio data is completed Y in step S 3 , the main processing section 11 instructs the interrupt controller 17 to mask an interruption having a lower priority than reception of radio data step S 4.
This prevents exception handling from occurring by an interruption having a lower priority than reception of radio data, which would otherwise rewrite the program stored in the command cache Next, the sub-processing section 12 of the CPU 10 accesses the external memory 40 via the bus interface 15 , and stores an internal operation program module which does not access the external memory in the command cache 13 step S 5.
After storage of the internal operation program, the main processing section 11 of the CPU 10 carries out a process of receiving radio data step S 6. The CPU 10 has nothing to do with the actual reception of the radio data itself which is executed by the radio section 30 , but performs data processing after data reception.
When reception of the radio data is completed Y in step S 7 , the main processing section 11 unmasks the interruption that has a lower priority than reception of radio data step S 8 and returns to the normal operation after which the CPU 10 processes the received data. At the time of data reception, the CPU 10 operates according only to an internal operation program stored in the internal command cache 13 and does not access the external memory.
The CPU 10 can therefore execute another process within the capability of a program which is storable in size in the internal command cache